FPGA Provides Speedy Data Compression for Hyperspectral Imagery

Current spaceborne NASA hyperspectral imaging instruments either avoid onboard compression or make use of only limited lossless image compression techniques during transmission. For example, the current state-of-practice for low-complexity space-qualified lossless compression hardware is to use the Universal Source Encoder for Space (USES) chip [1]. The USES chip implements the onedimensional Rice coding compression algorithm, as formalized in a standard produced by the consultative committee for space data systems (CCSDS) [2]. The use of a spectral prediction as a preprocessing step allows one to exploit correlations among spectral bands of a hyperspectral image. This approach provides radiation-resistance using currently available hardware, but it achieves limited compression effectiveness compared to state-of-the-art techniques designed specifically for hyperspectral imagery. Software solutions on traditional single core space CPU have limited throughput performance and are power hungry. Multi-core and GPU implementations of the data compression algorithm provide nearly real-time solutions but the hardware is not yet qualified for space [3]. Dedicated hardware solutions are highly desirable, taking load off the main processor while providing a power efficient solution at the same time. VLSI ASIC implementations are powerand area-efficient, but they lack flexibility for postlaunch modifications and repair, they are not scalable and cannot be configured to efficiently match specific mission needs and requirements. FPGAs are programmable and offer a low cost and flexible solution compared to traditional Application-Specific Integrated Circuit (ASICs).